용어 설명 (전자,전기 계통)
 

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ABSOLUTE ACCURACY.
A measure of the uncertainty of an instrument reading compared to that of a primary standard having absolute traceability to the National Institute of Standards and Technology. It is expressed in ppm. Accuracy is often separated into gain and offset terms. See also RATED ACCURACY.
ACCEPTOR.
A material added as a dopant to a semiconductor to make it p-type by "accepting" valence electrons, leaving "holes" behind in the valence band that can conduct electric charge. Boron is an acceptor dopant for silicon.
ACCUMULATION REGION.
The region of the curve in which majority carriers are attracted to the semiconductor-insulator interface. In this region, Ch and Cq both "flatten out" to Cox.
ACID.
Corrosive materials whose water solutions contain hydrogen ions (H+). Like bases, in sufficient amounts, these materials burn, irritate, or destructively attack organic tissues, such as skin, lungs, and stomach.
ACQUISITION RATE.
The rate at which the board acquires analog or digital data from an external signal input to the board. In the case of a scanning A/D, this is the aggregate conversion rate for all channels. (Number of channels times the sample rate per channel.)
A/D.
Abbreviation for analog-to-digital.
A/D (ANALOG-TO-DIGITAL) CONVERTER.
An electronic device, often an integrated circuit, that converts an analog voltage to a digital value. All digital instruments use an A/D converter to convert the input signal into digital information.
ADMITTANCE.
The reciprocal of the impedance. The admittance is the complex ratio of the current flowing through divided by the voltage across a device, circuit element, or network.
ACTUATION TIME.
The time between application of the nominal relay coil voltage and the final closure of the relay contacts after the contact bounce interval. Also called operate time.
ALIASING.
Where the sampling rate is less than twice the input signal's highest frequency content.
ANALOG OUTPUT.
An output that provides an analog signal derived from the digital information within the instrument.
ANALOG RAMP.
A voltage output of constant slope, dV/dt (Volts/second).
ANALOG TRIGGER.
An event that occurs at a user-selected point on an analog input signal. The polarity, sensitivity, and hysteresis of the analog trigger can often be programmed. See also TRIGGER,TRIGGER CONDITIONS, TRIGGER HYSTERESIS, TRIGGER MODE, TRIGGER POLARITY, and TRIGGER SENSITIVITY.
ANALYSIS CONSTANTS.
All scalar parameters in the Keithley C-V test, including user inputs like Cox, Area, tox, and Nbulk and derived parameters like Vth, Vfb, and Navg.
ANGSTROM.
A unit of length equal to 10-10 meters. Thus, there are ten angstroms to one nanometer (nm).
ANNEALING.
The process of heating a device or material in order to repair damage to the crystal lattice or activate dopant atoms.
APERTURE JITTER.
The short-term variation of aperture time.
APERTURE TIME.
The time interval during which an amplifier or measuring instrument acquires a sample of the signal. Also known as the sample window.
APPLICATION PROGRAM.
A computer program used to perform a particular kind of work, such as data acquisition. Examples of application programs include high-level packages such as VIEWDAC or user programs written using function call drivers or low-level calls.
APPLICATION SPECIFIC EFFECTS. (PARAMETRIC TESTING)
Charge to breakdown of node dielectric. Change in parameter matching.
APPLICATION SPECIFIC PARAMETERS. (PARAMETRIC TESTING)
Special parameters related only to a specific product. Term is applicable to CMOS or bipolar devices.
ASYNCHRONOUS.
In hardware, it is an event that occurs independent of other events; it is not synchronized with a clock signal. In software, it refers to a function that begins an operation and returns to the calling program prior to the completion or termination of the operation.
AUTO-IGNITION TEMPERATURE (AT).
The temperature at which a gas or vapor can explode or burst into flames with no other source of ignition.
AUTOPOLARITY.
The ability of an instrument to measure and display an input of either polarity without switching the input leads.
AUTORANGING TIME.
For instruments with autoranging capability, the time interval between application of a step input signal and its display, including the time for determining and changing to the correct range.
AUTORANGING.
The ability of an instrument to switch among ranges automatically. The ranges are usually in decade steps.
AVALANCHE BREAKDOWN.
A breakdown that is caused by the cumulative multiplication of charge carriers through field-induced impact ionization.
AVERAGE RESPONDING.
A measurement where the displayed value is proportional to the average of the absolute values of all input waveforms within a specified frequency range. It is calibrated in the rms value of a sine wave.

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BACK END.
Back-end refers to the package assembly and test stages of production in semiconductor manufacturing. It includes burn-in and environmental test functions.
BACKGROUND TASK.
An operation that can take place while another program or processing routine is running without apparent interruption to that program or routine. For example, an interrupt or DMA operation.
BAND BENDING.
The increase or decrease of the energy band at the interface between materials (such as semiconductor/insulator). Carriers will experience an electric field where the energy band bends and fall down or float up, depending on type.
BANDWIDTH.
The highest frequency signal component that can pass through input amplifiers and/or filters without being attenuated.
BANDWIDTH. (DATA ACQUISITION)
The range of frequencies that can be switched, conducted, or amplified within certain limits. Under given load conditions, bandwidth is defined by the -3dB (half-power) points.
BANK.
A group of relays with a common connection for scanning or multiplexing applications.
BASE.
Corrosive materials whose water solutions contain hydroxyl ions (OH-). Like acids, in sufficient amounts, these materials burn, irritate, or destructively attack organic tissues such as skin, lungs, and stomach.
BASE ADDRESS
An I/O address that is the starting address for programmable registers. All subsequent registers are accessed by adding to the base address.
BETA.
The ratio of the collector current to the base current of a bipolar transistor, commonly referred to as either the common-emitter current gain or the current amplification factor.
BIAS VOLTAGE
A voltage applied to a circuit or device to establish a reference level or operating point of the device during testing.
BIAS TEMPERATURE STRESS (BTS) CYCLE.
The stress cycle consists of a bias voltage applied while the device is heated to a stress temperature for a duration called the stress time.
BIAS TEMPERATURE STRESS (BTS) TEST.
A test for mobile ion drift consisting of C-V curves alternated with positive and negative voltage BTS cycles.
BICMOS.
Bipolar Complementary Metal Oxide Semiconductor. An IC technology combining the linearity and speed advantages of bipolar and the low-power advantages of CMOS on a single IC. BiCMOS can operate at either ECL (emitter-coupled-logic) or TTL (transistor-transistor-logic) levels, and is ideal for mixed-signal devices.
BIMOS.
Bipolar Metal Oxide Semiconductor. A general term to refer to bipolar and MOS on one chip. Sometimes used interchangeably with "BiCMOS."
BIPOLAR.
An analog signal range that includes both positive and negative values.
BIPOLAR TRANSISTOR.
An active semiconductor device formed by two P-N junctions whose function is amplification of an electric current. Bipolar transistors are of two types: NPN and PNP and have three sections: emitter, base, and collector. Operation of a bipolar transistor depends on the migration of both electrons and holes, in contrast to field-effect transistors, where only one polarity carrier predominates.
BIT-MAPS. (PARAMETRIC TESTING)
A yield parameter. Number and location of defective bits in DRAM or SRAM sub-arrays.
BREAK-BEFORE-MAKE.
Disconnecting the present circuit before connecting a new circuit.
BUFFER MEMORY.
Temporary storage area for acquired or generated data. See also LOCAL BUFFER.
BURN-IN.
The operation of items prior to their ultimate application, intended to stabilize their characteristics and identify early failures.
BURST MODE.
A data acquisition mode in which a group of analog input channels are scanned at an interval determined by the pacer clock and the signal from each channel within the scan is converted at a higher rate determined by the burst mode conversion clock. This mode minimizes the skew between channels.
BUS.
An interconnection system that allows each part of a computer to communicate with the other parts.
BYTE.
A group of eight bits.

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C-T.
Capacitance vs. time. Generally, this means the measurement of the capacitance transient that follows a voltage step on the MIS capacitor gate from accumulation or depletion into inversion.
C-V.
Capacitance vs. Voltage. The relationship or curve of capacitance vs. voltage of a device. Generally measured on Schottky, p-n, or MIS structures. C-V curves are of interest to ascertain device geometry, internal device potentials, and device charges.
C-V DOT.
A conducting dot (usually aluminum) evaporated onto a wafer as the gate connection of a MIS device for C-V testing.
C-V METER.
An instrument that measures capacitance (and usually conductance) as a function of voltage for semiconductor device test. For optimum testing, the capacitance test signal level should be less than 50mVrms and the voltage source should be coordinated with the meter during staircase and step waveforms.
CABLE CALIBRATION, CABLE CORRECTION, CABLE COMPENSATION.
A method of correcting for errors in high frequency capacitance measurements due to cables connecting the device under test (DUT) to the instrument. The cables (or other connection devices, such as switches and probers) have series resistance and inductance, shunt capacitance, and phase delay, which cause the errors.
CABLE CORRECTION USING REFERENCE CAPACITORS.
In this method, precise capacitance references are measured through the connecting cables to determine their S-parameters. The instrument uses the S-parameters to correct for cable errors.
CAPACITANCE.
In a capacitor or system of conductors and dielectrics, the property that permits the storage of electrically separated charges when potential differences exist between the conductors. Capacitance is related to charge and voltage as follows: C = Q/V, where C is the capacitance in farads, Q is the charge in coulombs, and V is the voltage in volts.
CAPACITANCE METER.
Any meter that measures capacitance. Most capacitance meters do not have test signal levels appropriate for C-V testing and do not contain a staircase voltage source.
CAPACITANCE NON-LINEARITY.
A relationship between the actual and measured capacitance across a range that cannot be described with a straight line. The most common source of non-linearity is connection or cable error. See also CABLE COMPENSATION.
CAPACITANCE VOLTAGE.
The relationship (or curve) of capacitance versus voltage for a device. Generally measured on Schottky, P-N, or MIS structures. C-V curves are of interest to ascertain device geometry, internal device potentials, and device charges.
CAPACITIVE DISPLACEMENT CURRENT.
The current that flows in a capacitor in response to a voltage change across the capacitor.
CAPACITIVE LOAD DRIVE.
The maximum capacitance a digital-to-analog converter can drive without generating extraneous outputs.
CARRIER CONCENTRATION.
The concentration in cm-3 of free carriers. This is essentially a synonym for doping concentration. Strictly speaking, though, electrical techniques such as C-V measure carrier concentration because it is the electrical carriers we detect, not the chemical presence of dopant ions.
CARRY CURRENT.
The maximum continuous current of closed relay contacts. Most relays are rated higher for carry current than switched current. (Heat is generated by I2R losses for carry current and I2R losses plus arcing for switched current.) See also SWITCHED CURRENT.
CHANNEL (SEMICONDUCTORS).
The conducting region between a FET source and drain that is controlled by the applied gate voltage. The majority carriers are holes in P-channel FETs and electrons in N-channel FETs.
CHANNEL (SWITCHING).
One of several signal paths on a switching card. For scanner or multiplex cards, the channel is used as a switched input in measuring circuits or as a switched output in sourcing circuits. For switch cards, each channel's signal paths are independent of other channels'. For matrix cards, a channel is established by the actuation of a relay at a row and column crosspoint. See also PATH.
CHANNEL-GAIN QUEUE.
A user-defined sequence of channels with corresponding gains.
CHANNEL ISOLATION.
On a switching card, the isolation from signal high and low of one channel to signal high and low of any other channel (or the output on switch or scanner cards). Specified as resistance and capacitance, except for RF cards (decibels and frequency range). See also PATH ISOLATION.
CHARGE CARRIER.
A carrier of electric charge. An electron carries negative charge and a hole carries positive charge. Charge carriers are free to move through the semiconductor device.
CHARGE COUPLED DEVICE (CCD).
A semiconductor device, often used for sensing light, which operates by storing charge on capacitors and selectively moving that charge through the device by manipulating voltages on its electrodes.
CIF FILE.
An ASCII based file format used to store and transfer graphical microcircuit design information.
CMOS.
Complementary Metal-Oxide Semiconductor. A MOS technology in which both P-channel and N-channel components are fabricated on the same die to provide integrated circuits that use less power than those made with other MOS or bipolar processes.
COIL RESISTANCE.
A nominal value of the resistance of a relay coil winding at a specified ambient temperature.
COLD JUNCTION.
The junction in a thermocouple circuit that is held at a stable known temperature. Also known as reference junction.
COLD-JUNCTION COMPENSATION.
A method of compensating for ambient temperature variations in thermocouple circuits.
COLD SWITCHING.
Closing the relay contacts before applying voltage and current and removing voltage and current before opening the contacts. (Contacts do not make or break current.) See also DRY CIRCUIT SWITCHING.
COLUMN.
As viewed on the schematic of a matrix relay card, the vertical signal lines or a vertical group of relays.
COMBUSTIBLE LIQUID.
Materials with a flash point above 37.8°C (100°F).
COMMON MODE INPUT ISOLATION.
On a switching card, the isolation from signal high and low to guard (or shield) for a 3-pole circuit, or from signal high and low to chassis ground for a 2-pole circuit. Specified as resistance and capacitance.
COMMON MODE REJECTION RATIO (CMRR).
The ability of an instrument to reject interference from a common voltage at its input terminals with respect to ground. Usually expressed in decibels at a frequency.
COMMON MODE VOLTAGE.
A voltage between input low and chassis ground of an instrument.
COMPLIANCE CURRENT.
The maximum output current of a constant voltage source. Also known as current limit.
COMPLIANCE VOLTAGE.
The maximum output voltage of a constant current source. Also known as voltage limit.
COMPOUND SEMICONDUCTOR.
A semiconductor material made up of elements from different columns of the periodic table, such as columns III and V or II and VI. III-V semiconductors include gallium arsenide and indium antimonide. II-VI semiconductors include zinc sulfide and cadmium sulfide.
CONDUCTANCE (G).
The ability to conduct electricity. Defined by G = Re (I/V) where G is the conductance in Siemens, I is the current in Amps, and V is the voltage in Volts.
CONDUCTION BAND.
The next higher energy band above the valence band. This represents the energy of charge carriers that have surmounted the energy bandgap and are free to move throughout the material.
CONDUCTIVITY TYPE.
n-type or p-type. In n-type extrinsic semiconductor material, electrons are the majority charge carrier. In p-type, extrinsic semiconductor material, holes are the majority charge carrier.
CONDUCTOR OPENS. (PARAMETRIC TESTING)
A yield parameter. Estimated number of interrupted conductors as a function of width.
CONDUCTOR SHORTS. (PARAMETRIC TESTING)
Estimated number of bridging conductors as a function of space.
CONNECTION PATH.
The cables, connectors, switch cards, etc. between the device under test (DUT) and the instrumentation. Its major parts are the conductors making the connection and the insulators isolating the conductors from the rest of the world.
CONTACT BOUNCE.
The intermittent and undesired opening of relay contacts during closure, or closing of relay contacts during opening.
CONTACT LIFE.
The maximum number of expected closures before failure. Life is dependent on the switched voltage, current, and power. Failure is usually when the contact resistance exceeds an end of life value.
CONTACT OFFSET VOLTAGE.
See CONTACT POTENTIAL.
CONTACT OPENS. (PARAMETRIC TESTING)
A yield parameter. Estimated number of missing contacts in a specific contact chain.
CONTACT POTENTIAL.
A voltage produced between contact terminals due to the temperature gradient across the relay contacts, and the reed-to-terminal junctions of dissimilar metals. (The temperature gradient is typically caused by the power dissipated by the energized coil.) Also known as contact offset voltage. See THERMOELECTRIC VOLTAGE.
CONTACT RATING.
The voltage, current, and power capacities of relay contacts under specified environmental conditions. See CARRY CURRENT and SWITCHED CURRENT.
CONTACT RESISTANCE.
For a relay, the resistance in ohms across closed contacts. For a Keithley switching card, also includes the tape resistance and connector terminal resistance. See also PATH RESISTANCE.
CONTACT RESISTANCES. (PARAMETRIC TESTING)
Resistance per contact. CMOS or bipolar device parameter.
CONTAMINATION.
Generally used to describe the unwanted material that adversely affects the physical, chemical, or electrical characteristics of a semiconductor device.
CONTINUOUS C-t.
Capacitance vs. time measured by applying a stimulus (usually a voltage step) once, then directly measuring the capacitance response in real time.
CONVERSION.
A process where a signal is changed from an analog to digital (A-D) representation, or digital to analog (D-A).
CONVERSION RATE.
The rate at which sampled analog data is converted to digital data or digital data is converted to analog data.
CONVERSION TIME.
The time required to complete an analog to digital or digital to analog conversion.
CORROSION.
An unwanted electrochemical process that affects device (e.g., semiconductor) reliability.
CORROSIVE MATERIAL.
A material that can attack (corrode) metals or cause permanent damage to human tissues such as skin and eyes on contact.
COUNTER/TIMER.
A circuit that counts pulses or measures pulse duration.
CREST FACTOR.
The ratio of the peak value to the root-mean-square (rms) value of a waveform.
CROSSPOINT.
The intersecting point of a column and row in a relay matrix. Specified as (column,row) or (row,column). A crosspoint generally consists of one or more poles of Form A (normally open) relay switching.
CROSSTALK.
The coupling of a signal from one input to another (or from one channel to another or to the output) by conduction or radiation. Crosstalk is expressed in decibels at a specified load and up to a specific frequency.
CURRENT GAINS. (PARAMETRIC TESTING)
A bipolar device parameter. Ratio of collector to base (beta) or collector to emitter (alpha) currents.

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D/A.
Abbreviation for digital-to-analog.
D/A (DIGITAL-TO-ANALOG) CONVERTER.
An electronic device, often an integrated circuit, that converts a digital value to an analog voltage. D/A converters are used in many instruments to convert digital reading information into an analog signal for analog output.
DC PARAMETRICS.
The operating characteristics of an integrated circuit or discrete device that can be measured with the device in a static condition.
DARK BOX.
An opaque enclosure placed around a test fixture or prober to keep the device under test from exposure to light. Typically, the dark box is metallic and, thus, also provides electrostatic shielding.
DATA TRANSFER.
Refers to the way data is transferred to and from memory, such as programmed I/O or DMA mode.
DEEP DEPLETION.
The phenomenon of driving the space charge or depletion region of the semiconductor material deeper than in equilibrium by sweeping or stepping the voltage quickly in the direction from accumulation toward inversion.
DEEP LEVEL TRANSIENT SPECTROSCOPY (DLTS).
An advanced technique for studying the interface dynamic, not just density. Along with Dit, DLTS measures trap capture cross-section.
DEPLETION LAYER.
The region of a semiconductor device where essentially all charge carriers are swept out by an electric field.
DEPLETION.
The region of operation in a MIS capacitor where the majority carriers are depleted from the surface.
DEPLETION APPROXIMATION.
A type of doping profile calculation from a C-V that only takes into account the theory of depletion operation (not accumulation or inversion). Because of this approximation, it is not accurate at very small or great depths. See MAJORITY CARRIER CORRECTION METHOD.
DEPLETION LAYER.
The volume of semiconductor material under the gate that is depleted of majority carriers. This occurs in the depletion region of the C-V curve.
DEPLETION REGION.
The center region of the C-V curve, where both high frequency and quasistatic capacitance decline from accumulation toward inversion. This region is the most important for C-V analysis and most MIS device operation.
DEPOSITION.
The procedure in which materials are deposited onto a substrate by means of vacuum, electrical, chemical, screening or vapor techniques.
DEPTH.
The distance between the semiconductor-insulator interface and the depletion layer edge.
DEVICE HANDLE.
A name that uniquely identifies a hardware device in an application program.
DICE, DIE.
A section of a processed wafer, usually rectangular, which contains one functional circuit. After processing, the wafer is sawed into die, which are then packaged.
DIELECTRIC.
An insulating layer. A material that has high resistance. This term is usually used when the insulating layer separates the plates of a capacitor.
DIELECTRIC ISOLATION (DI).
A method of isolating individual regions in an integrated circuit, particularly a bipolar IC, by surrounding the region with insulating material (dielectric) rather than with isolating diffusions.
DIELECTRIC PERMITIVITY.
The constant of proportionality between a capacitor's geometry and its capacitance.

capacitance = (dielectric permitivity) * area / dielectric thickness

DIFFERENTIAL INPUT ISOLATION.
On a switching card, the isolation from signal high to low. Specified as resistance and capacitance.
DIFFERENTIAL INPUTS.
An analog input with two input terminals, neither of which is grounded, whose value is the difference between the two terminals. See also SINGLE-ENDED INPUTS.
DIFFERENTIAL NON-LINEARITY.
The maximum deviation of an actual quantized step width from the ideal quantized step width. See QUANTIZATION.
DIFFUSION.
A process used in semiconductor production for adding small amounts of impurities or dopants to a semiconductor material by exposing its surface at high temperature and allowing it to seep or "diffuse" in.
DIFFUSION METHOD.
Diffusion methods place a sensor at the point of measurement and expose it directly to a gas.
DIGITAL I/O.
Abbreviation for digital input/output.
DIGITAL LINES/PORTS/BITS/CHANNELS.
In hardware, a digital line is physical hardware connection to a pin with a digital signal. A digital port is a physical grouping of digital lines. In software, a digital bit (1 or 0) is a logical representation of a digital line. A digital channel is a logical grouping of digital bits.
DIGITAL TRIGGER
An event that occurs at a user-selected point on a digital input signal. The polarity and sensitivity of the digital trigger can often be programmed. See also TRIGGER, TRIGGER CONDITIONS, TRIGGER POLARITY, and TRIGGER SENSITIVITY.
DIODE BREAKDOWN VOLTAGE.
The voltage under specified conditions at which there is a sudden change from high dynamic resistance to a much lower value.
DIRECT DIGITAL SYNTHESIS.
A technique for signal generation where the signal is directly synthesized using only digital techniques. This technique generates very precise waveforms, even at low frequencies. Waveforms with correct phase and frequency are obtained immediately after a shift to a new frequency.
DISCRETE DEVICE.
A class of electronic components that contain one active element, such as a transistor or diode. However, hybrids, optoelectronic devices, and intelligent discretes may contain more than one active element.
DISPLACEMENT CURRENT.
The current that flows through a capacitor in response to the rate of voltage change across it:

displacement current = C * dV/dt

DMM.
An electronic instrument that measures voltage, current, resistance, or other electrical parameters by converting the analog signal to digital information and display. The typical five-function DMM measures DC volts, DC amps, AC volts, AC amps, and resistance.
DMA (DIRECT MEMORY ACCESS) CHANNELS.
ISA bus PCs offer eight parallel channels for DMA mode data transfers. A number of these are reserved for exclusive use by the computer. The remainder are available for use by user-supplied I/O options, such as plug-in data acquisition cards. Also called DMA levels.
DMA MODE.
Mode in which data transfers directly between an I/O device and computer memory. The CPU is bypassed. See also OPERATION MODES.
DONOR.
A material added as a dopant to a semiconductor to make it n-type by "donating" valence electrons, which can conduct electric charge. Phosphorus is a donor dopant for silicon.
DOPANT.
A material added in minute quantities (about 1ppm) to a semiconductor to alter its electrical conductivity type. Dopants may be donors or acceptors.
DOPING.
The process of adding dopants to a semiconductor material.
DOPING PROFILE.
The profile or distribution of dopants in the semiconductor material. In other words, the graph of dopant concentration at each depth into the semiconductor device.
DRAIN TERMINAL.
Along with the source and gate, one of the three terminals of a field effect transistor (FET).
DRAM.
Dynamic Random Access Memory. A semiconductor read/write memory chip, in which the presence or absence of a capacitive charge represents the state of a binary storage element (zero or one). The charge must be periodically refreshed.
DRIFT.
A gradual change of a reading with no change in the input signal or operating conditions.
DRIVERS.
Software that controls a specific hardware device such as a data acquisition board.
DRIVING POINT CABLE CORRECTION.
A method of correcting for errors in high frequency capacitance measurements due to cables connecting the DUT to the instrument. In this method, the cable impedance is measured by the instrument with the DUT end open.
DRY CIRCUIT SWITCHING.
Switching below specified levels of voltage (e.g., 20mV) and current to minimize any physical and electrical changes in the contact junction. See also COLD SWITCHING.
DRY REED RELAY.
A glass-enclosed, hermetically sealed, magnetically actuated contact. No mercury or other wetting material is used.
DSP.
Abbreviation for Digital Signal Processing.
DUAL IN-LINE PACKAGE (DIP).
A plastic or ceramic package with two rows of vertical leads.
DUTY RATIO.
The ratio of pulse width to repetition period. Also known as Duty Cycle.
DYNAMIC DATA EXCHANGE (DDE).
A Microsoft Windows standard mechanism for communication between programs. It allows your application to send and share data with other applications such as spreadsheets.
DYNAMIC LINK LIBRARY (DLL).
A software module in Microsoft Windows containing executable code and data that can be called or used by Windows applications or other DLLs. DLL functions and data are loaded and linked at run time when they are referenced by a Windows application or other DLLs.

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EARLY VOLTAGES. (PARAMETRIC TESTING)
A bipolar device parameter. Voltage intercept of slope of collector current versus collector voltage.
EEPROM OR EPROM.
Electrically-Erasable Programmable Read-Only Memory. Similar to PROM, but with the capability of selective erasure of information through special electrical stimulus. Information stored in EEPROM chips is retained when the power is turned off.
EFFECTIVE BASE WIDTH. (PARAMETRIC TESTING)
A bipolar device parameter. Base width at specified collector/base voltage.
EFFECTIVE CHANNEL LENGTHS, LINEAR. (PARAMETRIC TESTING)
A CMOS device parameter. Electrical channel length from scaling devices, small drain voltage.
EFFECTIVE CHANNEL LENGTHS, SATURATION (PARAMETRIC TESTING)
A CMOS device parameter. Electrical channel length from self-consistency, large drain voltage.
EFFECTIVE CHANNEL WIDTH. (PARAMETRIC TESTING)
Electrical channel width from scaling devices, small drain voltage.
EISA BUS.
Extended Industry Standard Architecture. A 32-bit wide, upwards-compatible extension of the 16-bit wide ISA bus. Sometimes called the XT bus.
ELECTROMETER.
A highly refined DC multimeter. In comparison with a digital multimeter, an electrometer is characterized by higher input resistance and greater sensitivity. It can also have functions not generally available on DMMs (e.g., measuring electrical charge, sourcing voltage).
ELECTROMIGRATION. (PARAMETRIC TESTING)
Maximum current allowed before specified change in resistance occurs.
ELECTRON.
A negatively charged particle revolving round the nucleus of an atom.
ELECTRON AFFINITY.
The energy required to move an electron from the bottom of the semiconductor conduction band to the vacuum energy level, i.e. to infinity. This number is used in the calculation of work function in devices with polysilicon gates.
ELECTRON, FREE.
An electron not bound to the crystalline lattice, hence, free to conduct electricity.
ELECTRON-HOLE PAIR (EHP).
The electron and hole that are simultaneously generated thermally or optically. Once generated, the pair can either recombine and disappear or separate and conduct charge as independent free carriers.
ELECTROSTATIC DISCHARGE. (PARAMETRIC TESTING)
Voltage pulse on protective structure in parallel to protected gates. Related to reliability.
ENERGY BAND.
The specific levels of energy that charge carriers (electrons or holes) in a solid are permitted to have. Carriers cannot have an energy outside the allowed energy band.
EPITAXY.
The process of growing a single crystal film onto another crystalline substrate or layer. The resulting "epitaxial layer" is sometimes referred to as "epi."
EPITAXIAL LAYER.
A deposited layer of material having the same crystallographic characteristics as the substrate material.
EQUILIBRIUM.
The condition in a semiconductor device or material when there is no longer any tendency for its macroscopic properties to change with time. In other words, everything that is going to happen has happened. Specifically, in an MOS capacitor, current ceases to flow and the capacitor is fully charged.
ERROR.
The deviation (difference or ratio) of a measurement from its true value.
EXPLOSIVE.
A chemical that causes a sudden, almost instantaneous release of pressure, gas, and heat when subjected to sudden shock, pressure or high temperature.
EXPLOSIVE (FLAMMABLE) LIMITS.
The Lower Explosive Limit (LEL) is the lowest concentration of vapor in air that will burn or explode upon contact with a source of ignition. The Upper Explosive Limit (UEL) is the highest concentration of vapor in air that will burn or explode upon contact with a source of ignition.
EXPLOSIVE (FLAMMABLE) RANGE.
The range between the Lower Explosive Limit (LEL) and the Upper Explosive Limit (UEL).
EXTERNAL TRIGGER.
An analog or digital hardware event from an external source that starts an operation. See also INTERNAL TRIGGER.
EXTRINSIC BASE RESISTANCES. (PARAMETRIC TESTING)
A bipolar device parameter. Base resistance outside active base.
EXTRINSIC CHANNEL RESISTANCES. (PARAMETRIC TESTING)
A CMOS device parameter. Sum of all resistances between channel and source/drain connections.
EXTRINSIC SEMICONDUCTOR.
A semiconductor that has been doped either n-type or p-type. Electrons and holes are present in unequal proportions (by 4 to 8 orders of magnitude).

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FAB.
In semiconductor manufacturing, fabrication usually refers to the front-end process of making devices and integrated circuits in semiconductor wafers, but does not include the package assembly back-end) stages.
FALL TIME.
The time required for a signal to change from a large percentage (usually 90%) to a small percentage (usually 10%) of its peak-to-peak amplitude. See also RISE TIME.
FEEDBACK CHARGE QUASISTATIC C-V METHOD.
A method for measuring quasistatic C-V, developed by Keithley Instruments, based on stimulation by a DC voltage step and measurement of charge by a differential feedback charge meter. Its fundamental calculation is:

Quasistatic C = charge step / voltage step

FERMI LEVEL.
The energy level in the semiconductor device at which the probability of finding an electron is 50%. In other words, it's like the water level in a glass. States below the Fermi level are full and those above it are empty.
FIELD EFFECT TRANSISTOR (FET).
A transistor consisting of a gate, source, and drain. The voltage applied to the gate controls the conductivity of the channel between the source and drain. Examples of FETs are the MOSFET, JFET, and MESFET.
FIELD OXIDE THRESHOLD VOLTAGE. (PARAMETRIC TESTING)
A CMOS device parameter. Voltage at 40nA*W/L or predefined current, thick-oxide MOSFETs.
FIFO.
First-in/first-out memory buffer. The first data into the buffer is the first data out of the buffer.
FIXED OXIDE CHARGE.
Charge trapped in the insulator of an MIS device that cannot move to the semiconductor material. Unlike oxide trapped charge, fixed oxide charge does not anneal out during a BTS cycle. This charge may be located at either oxide interface and is commonly produced by carrier injection or radiation. See also OXIDE TRAPPED CHARGE.
FLASH MEMORY.
It is a non volatile memory technique with fast access times; rewriteable many times and uses a block erase technique as opposed to EEPROM, which erases one bit at a time.
FLATBAND VOLTAGE.
Theoretically, the gate to substrate voltage applied to an MIS device at which band bending is zero. In practical devices, non-uniformities prevent any one gate voltage from producing perfectly flat bands. However, for the purposes of measuring flatband voltage shift, use of the simplified definition produces meaningful, repeatable results to monitor mobile ionic charge.
FLATBAND VOLTAGE SHIFT.
The shift in flatband voltage induced through a BTS cycle. The magnitude of this shift is directly proportional to mobile ion contamination in the oxide.
FLOATING.
The condition where a common mode voltage exists between an earth ground and the instrument or circuit of interest. (Low of circuit is not at earth potential.)
FLOATING C-V MEASUREMENT.
A capacitance vs. voltage measurement in which neither terminal of the capacitor is grounded. Typically, this means one terminal (substrate) is stimulated with the test signal and the response is measured from the other (gate).
FOREGROUND TASK.
An operation, such as those that occur in the single or synchronous mode, that cannot take place while another program or routine is running.
FOUR-TERMINAL RESISTANCE MEASUREMENT.
A measurement where two leads are used to supply current to the unknown and two different leads are used to sense the voltage drop across the resistance.
FRAME.
A data structure that consists of one or more elements corresponding to an operation's defining attributes.
FREE CARRIER.
See CHARGE CARRIER.
FRONT END.
In semiconductor manufacturing, front end refers to the fabrication process in which the integrated circuit is formed in and on the wafer.
FUNCTION CALL DRIVER.
A type of Keithley MetraByte board driver which provides a high-level alternative to register-level programming.

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GAIN.
The factor by which an incoming signal is multiplied.
GATE.
A signal which in the active state enables an operation to occur; and when in the inactive state inhibits an operation from occurring.
GATE LEAKAGE CURRENT.
Because the gate is reverse biased with respect to the channel, the current flowing to the gate terminal is very small; it is the reverse bias leakage current of a p-n junction.
GATE LENGTH.
Physical distance between source and drain of a MOS transistor measured on the photomask plate. When determined from the actual transistor characteristics, called "effective" gate length.
GATE OXIDE.
The thin, high quality silicon dioxide layer in the MOSFET gate region.
GATE OXIDE, DIELECTRICS. (PARAMETRIC TESTING)
A parameter related to reliability. Integrated Fowler-Nordheim current through insulator up to "breakdown."
GATE TERMINAL.
Along with the source and drain, one of the three terminals of an FET. This term also applies to the MIS capacitor, which has only two terminals: the gate and substrate.
GDSII FILE.
A binary based file format used to store and transfer graphical microcircuit design information.
GENERATION LIFETIME.
The time required to generate one electron-hole pair by thermal emission processes. This time is measured using a C-t test and Zerbst analysis. More pure MOS devices have longer lifetime. Typical value 0.01 - 1 ms.
GLITCH ENERGY.
A glitch is an unwanted transient superimposed on the output of a digital-to-analog converter. Glitch energy is a measure of this transient. A simple figure of merit is an integral of the transient voltage with time. Also called glitch charge or glitch impulse.
GPIB.
Abbreviation for General Purpose Interface Bus. It is a standard for parallel interfaces.
GUARDING.
A technique that reduces leakage errors and decreases response time. Consists of a guard conductor driven by a low-impedance source surrounding the lead of a high-impedance signal. The guard voltage is kept at or near the potential of the signal.
GROUND.
A common reference point for an electrical system.
GROUNDED C-V MEASUREMENT.
A capacitance vs. voltage measurement in which one terminal of the capacitor is grounded. Typically, this means the capacitor gate is stimulated with the test signal and the response is also measured from the gate.

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HALL EFFECT.
The measurement of the transverse voltage across a conductor when placed in a magnetic field. By this measurement, it is possible to determine the type, concentration, and mobility of carriers in silicon.
HARDWARE.
The physical parts of a computer-controlled system, such as circuit boards, chassis, peripheral devices, cables, etc.
HAZARD.
The potential for harmful effects.
HAZARDOUS PRODUCTION MATERIAL (HPM).
A solid, liquid, or gas that has a degree-of-hazard rating in health, flammability or reactivity of Class 3 or 4 as ranked by Uniform Fire Code Standard No. 79-3 and that is used directly in research, laboratory, or production processes that have as their end product materials that are not hazardous.
HEAT SINK.
A part used to absorb heat.
HIGH FREQUENCY C-V.
A capacitance vs. voltage measurement obtained using such a high frequency test signal that neither minority carriers in the inversion layer nor interface traps can follow the AC gate voltage. Thus, they do not contribute to the high frequency capacitance.
HOLE.
The absence of an electron in the crystalline lattice. This absence behaves very much like a positively charged particle that can conduct electric charge.
HOT CARRIER DEGRADATION.
A parameter related to reliability. Accelerated test to predict lifetime. Typical indicator is change in IDSAT.
HOT CHUCK.
A platform or chuck, mounted on a prober onto which a wafer is placed for testing, which can be heated (typically to 150 - 300°C) for testing at elevated temperatures.
HOT JUNCTION.
The junction of two dissimilar metals in a thermocouple circuit that is used to measure an unknown temperature. Also known as measurement junction.

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IEEE.
Abbreviation for Institute of Electrical and Electronics Engineers.
IEEE-488.
See GPIB.
IMMEDIATELY DANGEROUS TO LIFE OR HEALTH (IDLH).
The (IDLH) concentration represents a maximum airborne concentration of a chemical from which, in the event of respirator failure, a person could escape within 30 minutes without any escape-impairing symptoms or any irreversible health effects. Unlike the TLV/PEL and STEL values, it is not a "safe" level of exposure.
IMPEDANCE.
The reciprocal of admittance. Admittance is the complex ratio of the voltage across divided by the current flowing through a device, circuit element, or network.
IMPURITY.
A material that is present in minute quantities in an ideally pure material. In the context of C-V testing, this term is synonymous with dopant.
INHALATION.
Taking a material into the body by breathing it in.
INPUT BIAS CURRENT.
The current that flows at the input due to internal circuitry and bias voltage. Also, the current that must be supplied to the high input measuring terminal (with zero input signal and offset voltage) to reduce the output indication to zero.
INPUT IMPEDANCE.
The shunt resistance and capacitance (or inductance) as measured at the input terminals, not including effects of input bias or offset currents.
INPUT ISOLATION.
On a switching card, the isolation from signal high to low (or guard) for a two-pole circuit. Specified as resistance and capacitance.
INPUT OFFSET CURRENT.
The difference between the two currents that must be supplied to the input measuring terminals of a differential instrument to reduce the output indication to zero (with zero input voltage and zero offset voltage).
INPUT OFFSET VOLTAGE.
The voltage that must be applied directly between the input measuring terminals, with bias current supplied by a resistance path, to reduce the output indication to zero.
INPUT/OUTPUT (I/O).
The process of transferring data to and from a computer-controlled system using its communication channels, operator interface devices, data acquisition devices, or control interfaces.
INSERTION LOSS.
The attenuation of signals due to routing them through a switching card. Specified as a decibel value over a frequency range.
ISOLATION LEAKAGE. (PARAMETRIC TESTING)
A CMOS device parameter. Isolated junction to junction current at maximum reverse voltage.
INSULATION RESISTANCE.
The ohmic resistance of insulation. It degrades quickly as humidity increases.
INSULATOR.
A material that does not significantly conduct electrical current. Insulators have wider bandgaps than semiconductor materials. Common insulators used in semiconductor processing include silicon dioxide (SiO2) and silicon nitride (Si3N4).
INTEGRATING CONVERSION.
An analog to digital conversion process where the output results in a digital representation of the integral of the input signal over a specified time interval.
INTERFACE TRAP DENSITY (Dit).
The probability per unit area that an interface trap level is present at a particular energy. The units of Dit are cm-2eV-1.
INTERFACE TRAPPED CHARGE.
Charge located on traps (defects, impurities) at the semiconductor-insulator interface. The trapping of charge otherwise involved on the operation of an MIS device lowers its efficiency, degrading such characteristics as gain, channel leakage, and noise.
INTERFACE TRAPS.
Defects in the semiconductor that allow for the trapping of charge between the valence and conduction band. The density of interface traps is referred to as DIT.
INTERLEVEL OXIDE.
Interlevel oxide is a layer of oxide that separates metal layers.
INTERLEVEL SHORTS. (PARAMETRIC TESTING)
A yield parameter. Estimated number of interlevel shorts per unit overlap area.
INTERNAL TRIGGER.
A software-generated event that starts an operation. See also EXTERNAL TRIGGER.
INTERRUPT.
A signal to the CPU indicating that the board detected the occurrence of a specified condition or event.
INTERRUPT LEVEL.
A specific priority that ensures that high priority interrupts get serviced before low priority interrupts.
INTERRUPT-MODE OPERATION.
Mode in which a data acquisition board acquires or generates samples using an Interrupt Service Routine (ISR). See also OPERATION MODES.
INTERRUPT SERVICE ROUTINE (ISR).
A software program that handles interrupts.
INTRINSIC SEMICONDUCTOR.
A pure semiconductor that has not been doped. Since it is not doped, it is neither n-type nor p-type and electrons and holes carry charge in equal concentrations.
INVERSION REGION.
The region of a C-V curve where high frequency capacitance is low and quasistatic is high. In this region, majority carriers are repelled from the semiconductor-insulator interface and minority carriers are attracted to it, building up and inverting the local conductivity type.
ION.
This is what an atom becomes when an electron is separated from the atom, leaving it with a net positive charge or, if an electron is added, leaving it with a net negative charge.
ION IMPLANTATION.
Introduction of dopant ions into a semiconductor material by accelerating them through a high voltage electric field and bombarding the semiconductor material. This doping process results in a layer of dopants buried in the semiconductor.
IRRITANT.
A chemical that is not a corrosive but that causes a reversible inflammatory effect on living tissue by chemical action at the site of contact.
ISA BUS.
Industry Standard Architecture. The 16-bit wide bus architecture used in most MS-DOS and Windows computers. Sometimes called the AT bus.
ISOLATED OUTPUTS.
Output signals where a common reference is not connected to either input terminal.

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JEDEC.
The engineering standardization body for solid state products in the US. The Solid State Products Division of the Electronics Industries Association is the sponsoring body for JEDEC.
JITTER.
The short-term variation of timed events. See APERTURE JITTER, TIMING JITTER, and TRIGGER JITTER.
JUNCTION AREA CAPACITANCES. (PARAMETRIC TESTING)
A CMOS or bipolar device parameter. Capacitance per unit area, as function of voltage.
JUNCTION AREA LEAKAGES. (PARAMETRIC TESTING)
A CMOS or bipolar device parameter or a yield parameter. Junction leakage per unit junction area.
JUNCTION FET (JFET).
A type of FET in which the gate forms a Schottky contact with the semiconductor material. C-V is not generally measured on this type of device.
JUNCTION PERIMETER CAPACITANCES. (PARAMETRIC TESTING)
A CMOS or bipolar device parameter. Isolation-sided or emitter/collector-sided leakage per unit length.
JUNCTION PERIMETER LEAKAGES. (PARAMETRIC TESTING)
A CMOS or bipolar device parameter. Leakage per unit isolation-sided and gate-sided perimeter.
JUNCTION PERIMETER LEAKAGES. (PARAMETRIC TESTING)
A yield parameter. Isolation-sided or emitter/collector-sided leakage per unit length.

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KELVIN CONTACTS.
A means for testing or making measurements in electronic devices and circuits, particularly when low values are being measured. Two sets of leads are used at each test point, similar with respect to thickness, material and length; one set carries the test signal and the other connects with the measuring instrument. The effect of resistance in the leads is thus eliminated.

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LATCH-UP.
A parameter related to reliability. Maximum current forced through any terminal before latch-up occurs.
LC50.
The concentration of a material in air that causes death in 50% of a group of test animals. The material is inhaled over a set period of time, usually 4 hours. LC stands for lethal concentration.
LCZ METER.
Inductance (L), capacitance (C), impedance (Z) meter. A general purpose instrument for measuring component L, C. and Z. Sometimes called LCR meter. This instrument may be applied to C-V testing, but typically lacks features optimized for C-V. See C-V METER.
LD50.
The weight of material that causes the death in 50% of a group of test animals. It is usually expressed in weight of material per weight of test animal. LD stands for lethal dose.
LEAKAGE CURRENT.
Error current that can degrade sensitive measurements. Leakage current is any unwanted current that flows when test voltage is applied. The ideal leakage current is zero. Leakage currents can originate in instruments, cables, or the device being tested. Even high resistance paths between low current conductors and nearby voltage sources can generate significant leakage currents.
LEAKAGE RESISTANCE.
The resistance calculated from the dependence of leakage current on applied voltage.

leakage resistance = V / leakage current

LEAST SIGNIFICANT BIT (LSB).
The lowest order bit in a digital quantity.
LIFETIME.
See GENERATION LIFETIME.
LINEARITY.
The maximum deviation from a straight line between instrument readings at zero and full range. It is expressed in ppm at a specific temperature.
LOCAL BUFFER.
Temporary memory location within an application program's memory area. It is always available to the application program. See also BUFFER MEMORY.
LONG-TERM ACCURACY.
The limit that errors will not exceed during a 90-day or longer time period. It is expressed as a percentage of reading (or sourced value) plus a number of counts over a specified temperature range.
LSTTL.
Schottky-clamp TTL logic typically using one-third the power of TTL, but maintaining TTL speeds. See also TTL.

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MAINFRAME.
A self-contained instrument in a cabinet, which provides a measurement or connection capability without requiring other instruments in the circuit. Some mainframes may be designated as a "master" or "slave." See also SWITCHING MAINFRAME, MASTER, and SLAVE.
MAJORITY CARRIER.
The type of free charge carrier that predominates in an extrinsic semiconductor material. For n-type, these are electrons (N means negative). For p-type, these are holes (P means positive).
MAJORITY CARRIER CORRECTION (MCC) METHOD.
A method for measuring doping profiles that corrects for the onset of accumulation at shallow depths. Also known as "the Ziegler method" after its creator.
MAKE-BEFORE-BREAK.
Connecting a new circuit before disconnecting the present circuit.
MASK.
A transparent plate covered with an array of patterns used in making integrated circuits. Each pattern consists of opaque and transparent areas that define the size and shape of all circuit and device elements. The mask is used to expose selected areas of photoresist, which defines areas to be etched.
MASTER.
A mainframe that has control of other mainframes (slaves) through an external connection. A slave unit adds capacity or functions to the master. The master/slave combination has one IEEE-488 bus address. See also SLAVE and MAINFRAME.
MATRIX CARD.
A type of card with a switching configuration that has columns and rows of relay crosspoints. (Also called a coordinate switch.) With a matrix card, since any one point can be connected to any other, you can simultaneously have one input with multiple outputs, multiple inputs with one output, or multiple inputs with multiple outputs.
MAXIMUM ALLOWABLE INPUT.
The maximum DC plus peak AC value (voltage or current) that can be applied between the high and low input measuring terminals without damaging the instrument.
MERCURY PROBE.
A type of probe for making electrical measurements on semiconductor wafers that uses a column of mercury as the gate contact or C-V dot.
MERCURY WETTED RELAY.
A reed relay in which the contacts are wetted by a film of mercury. Usually has a required operating position to avoid liquid mercury shorting the contacts; other types are position insensitive.
MESFET.
MEtal-Semiconductor FET. A type of FET that has a Schottky barrier as the gate electrode rather than a semiconductor junction and I-V characteristics similar to a junction FET.
METALLIZATION.
The process of depositing a thin film of conductive metal onto a substrate and patterning it to form the desired interconnection arrangement.
MICROMANIPULATOR, MICROPOSITIONER.
An apparatus for holding and positioning a probe to contact a semiconductor wafer.
MICRON.
A unit of length equal to 10-6 meters. Also called micrometer. There are 10,000 microns per centimeter.
MINORITY CARRIER.
The type of free charge carrier that does not predominate in an extrinsic semiconductor material. For n-type, these are holes and for p-type, these are electrons.
MINORITY CARRIER LIFETIME.
See GENERATION LIFETIME.
MIS.
Metal insulator semiconductor.
MIS CAPACITOR.
A device fabricated typically for testing purposes consisting of a semiconductor wafer, an insulator, and a metal gate.
METAL INSULATOR SEMICONDUCTOR FET (MISFET).
A type of FET in which the metal gate is insulated from the semiconductor material.
MOBILE ION CHARGE.
Charge present in the insulator or oxide of an MIS device, which under certain conditions will migrate, causing a shift in device characteristics. In silicon dioxide, sodium (Na+) and potassium (K+) are the predominant mobile ions.
MOBILITY.
A measure of the speed at which carriers move through doped semiconductor material per unit of electric field.
MOS.
Metal Oxide Semiconductor. A wafer process for fabricating MOSFET devices in either IC or discrete form.
MOS CAPACITOR.
A type of MIS capacitor in which the insulator is silicon dioxide and the semiconductor is typically silicon.
MOSFET.
A type of MISFET in which the insulator is an oxide. Typically Metal silicon diOxide Silicon.
MULTIPLE FREQUENCY.
At more than one frequency. This term is applied to a capacitance meter that offers a choice of discrete test signal frequencies.
MULTIPLEX.
Connecting one instrument to multiple devices under test or multiple instruments to one device under test. See also SCAN.

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N-TYPE.
The conductivity type of a semiconductor material when the majority of carriers are electrons, hence negative. N-type silicon is doped with dopant atoms from column V of the periodic table, such as phosphorus.
NANOVOLTMETER.
A sensitive DC voltmeter (typically one decade more sensitive than a digital multimeter) with a low thermal input connection.
NETWORK ANALYSIS.
The process of creating a model of the transfer or impedance characteristics of a linear network through stimulus-response testing over the frequency range of interest.
NOISE.
An undesirable electrical signal from an external source such as an AC power line, motors, generators, transformers, fluorescent lights, CRT displays, computers, radio transmitters, and others.
NON-EQUILIBRIUM.
The condition in a semiconductor device or material when there is still a tendency for its macroscopic properties to change with time. In other words, there still remains some settling to occur before equilibrium is achieved. Devices in which current always flows, like diodes and bipolar transistors, do not ever reach equilibrium.
NORMAL MODE REJECTION RATIO (NMRR).
The ability of an instrument to reject interference (usually of line frequency) across its input terminals. Usually expressed in decibels at a frequency.
NORMAL MODE VOLTAGE.
A voltage applied between the input high and input low terminals of an instrument.

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OBJECT LINKING AND EMBEDDING (OLE).
A Microsoft Windows standard mechanism for embedding one program within another. For example, an Excel spreadsheet can be pasted into a Visual Basic program. If a file is linked to an OLE control, the data stored in that file is displayed in the OLE control.
OCX.
Abbreviation for OLE Custom Control.
ODOR THRESHOLD.
The airborne concentration, usually in parts per million (ppm), at which an odor becomes noticeable.
OFF-CURRENTS, SATURATION. (PARAMETRIC TESTING)
A CMOS device parameter. Drain current at zero gate voltage, maximum drain voltage.
OFFSET CURRENT.
A current that comes from a switching card even though no user signals are applied. It comes mostly from the finite coil to contact impedance. It is also generated by triboelectric, piezoelectric, and electrochemical effects present on the card.
OHMIC CONTACT.
A resistive contact between a semiconductor material and metal. This type of contact exhibits a straight line I-V characteristic with a small value of resistance and does not significantly rectify.
OPERATION MODES.
Refers to single, synchronous, interrupt, DMA, and on-board memory (OBM) operations. See also DMA MODE and INTERRUPT-MODE OPERATION.
OPERATING SYSTEM.
Base-level software that organizes the computer's resources and capabilities, runs application programs, interacts with users, and communicates with installed and peripheral devices. Popular operating systems include DOS, Windows, OS/2, and UNIX.
OVERLAP CAPACITANCES.
A CMOS device parameter. Source/drain to gate capacitance per unit length.
OVERLOAD PROTECTION.
A circuit that protects the instrument against excessive current at the input terminals.
OXIDATION.
The growth of a layer of silicon dioxide on a silicon surface.
OXIDE.
A casual term for silicon dioxide (otherwise known as glass). This material is used in semiconductor processing as an insulator and to cover and protect or "passivate" the device.
OXIDE INTEGRITY.
The quality of the oxide. Oxide integrity testing often includes C-V, along with breakdown and reliability tests.
OXIDE THICKNESSES. (PARAMETRIC TESTING).
A CMOS device parameter. Equivalent thickness of thin, field, and inter-level dielectrics.
OXIDE TRAPPED CHARGE.
Charge trapped in the insulator of an MIS device that cannot move to the semiconductor material. Oxide trapped charge may anneal during a bias temperature stress cycle. Oxide trapped charge is located near the Si-SiO2 interface. See also FIXED OXIDE CHARGE.
OXIDIZER.
A chemical other than a blasting agent or explosive that initiates or promotes combustion by spontaneously evolving oxygen either at room temperature or under slight heating. These chemicals can react with organic material or intensify fires.

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P-TYPE.
The conductivity type of a semiconductor material when the majority of carriers are holes, hence positive. P-type silicon is doped with dopant atoms from column III of the periodic table, such as boron.
PACED MODE.
The sampling of each analog input channel at regularly spaced intervals. This interval is determined by the conversion rate of the analog-to-digital converter and the number of channels sampled (see CONVERSION RATE and SAMPLE RATE). In this mode, the conversion rate equals the pacer clock rate.
PACER CLOCK.
An on-board or external clock that paces or times events such as analog-to-digital conversions, digital-to-analog conversions, data sampling, interrupt generation, digital I/O transfers, etc.
PARALLEL C/G MODEL.
Interpretation of the real and imaginary components of admittance measured by a capacitance meter as conductance in parallel with capacitance.
PARAMETRIC TESTS.
Tests that measure DC conditions of a chip, such as maximum current, leakage, and output drive.
PARTS PER MILLION (PPM).
Represents the concentration of gases or vapor in air. For example, 1 ppm means that 1 unit of the gas is present for every 1 million units of air..
PASSIVATION.
Protection of the junctions and surfaces of solid state electronic components and ICs from harmful environments; most commonly achieved by forming a layer of silicon dioxide on the silicon chip.
PATH.
One of many signal paths on a matrix switching card. A path is established by the actuation of a relay at a row and column crosspoint. See also CHANNEL.
PATH ISOLATION.
On a matrix switching card, the isolation from signal high and low of one path to signal high and low of any other path. Specified as resistance and capacitance. See also CHANNEL ISOLATION.
PATH RESISTANCE.
On a matrix switching card, the resistance per conductor of a closed path, including the tape resistance and connector terminal resistance. See also CONTACT RESISTANCE.
PC.
Abbreviation for Personal Computer.
PCI.
Abbreviation for Peripheral Component Interconnect. It is a standard for a local bus.
PCMCIA.
Abbreviation for Personal Computer Memory Card International Association. This organization establishes standards for portable computers.
PEAK RESPONDING.
A measurement where the displayed value is equal to the peak value of the input signal.
PER CHANNEL RATE.
The sample rate for each channel of a scanning A/D system.
PERMISSIBLE EXPOSURE LIMITS (PEL).
Legal limits set by Occupational Safety and Health Administration (OSHA). See TLV.
PICOAMMETER.
A measuring instrument that is similar in function to the ammeter of an electrometer. General differences include: as low or lower voltage burden, faster readings, and less sensitivity.
PLASMA DAMAGE, CHARGING EFFECTS. (PARAMETRIC TESTING)
Typically, change in charge to breakdown and threshold voltage.
PN JUNCTION.
The interface between n-type and p-type semiconductor material. This structure forms a pn junction diode.
POLE.
A combination of mating relay contacts: normally open, normally closed, or both.
POLY, POLYCRYSTALLINE SILICON.
A form of silicon that is composed of many crystals. The silicon wafer is a single crystal. Poly can be formed by epitaxial deposition. It is often heavily doped to have high conductivity and is used in place of metal conductors.
PROBE TIP.
The tip of a probe for contacting a semiconductor device. The probe looks like a fine needle that is electrically connected to instruments. The probe is mechanically supported by a micropositioner.
PROBER.
An apparatus for contacting devices on semiconductor wafers. This includes a platen on which the micropositioner rests, a chuck on which the wafer rests, and a microscope for viewing small devices while positioning probes.
PROGRAMMED I/O.
A standard method of accessing an I/O device - the CPU reads each byte of data from or writes each byte of data to the device.
PULSED C-V.
Capacitance vs. Voltage measurements made by sweeping through a series of voltages from start to stop with the voltage returned after each point to a bias voltage level. The bias voltage is usually set in the accumulation or depletion region. Pulsed C-V is used to measure doping profiles deeper into the semiconductor device than with a staircase waveform.
PYROPHORIC.
A chemical that will ignite spontaneously in air at a temperature less than or equal to 54.4°C (130°F).

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QUANTIZATION.
A process where the continuous range of values of an input signal is divided into non-overlapping sub-ranges and, to each sub-range, a discrete value of the output is uniquely assigned.
QUASISTATIC C-V.
A Capacitance vs. Voltage measurement obtained using such a low frequency test signal that both minority carriers in the inversion layer and interface traps completely follow the AC gate voltage. Thus, they do contribute to the quasistatic capacitance.

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RADIATION HARDNESS.
The degree to which the characteristics of a device are stable despite exposure of the device to ionizing radiation.
RAMP QUASISTATIC C-V METHOD.
The traditional method for measuring quasistatic C-V. In this method, the substrate of an MIS capacitor is swept with an analog ramp and the capacitor's displacement current (I) is measured at the gate. Then, the capacitance is calculated using:

quasistatic C = I (dV/dt)

RANGE.
A continuous band of signal values that can be measured or sourced. In bipolar instruments, range includes positive and negative values.
RAPID THERMAL PROCESSING (RTP).
Processing semiconductor devices using higher temperatures and shorter processing times. Examples include rapid thermal annealing and rapid thermal oxidation.
RATED ACCURACY.
The limit that errors will not exceed when the instrument is used under specified operating conditions. It is expressed as a percentage (of input or output) plus a number of counts. See also ABSOLUTE ACCURACY.
RATIO MEASUREMENT.
The measurement of a signal input with relation to an external reference input.
READING.
The displayed number that is proportional to the measured magnitude of the input signal.
READING RATE.
The rate at which the displayed number is updated.
RECOVERY TIME.
The time required for an MIS capacitor to reach equilibrium in inversion after being pulsed from accumulation or depletion into deep depletion. The recovery time is directly proportional to the generation lifetime of the MIS device.
RELAY MUST-OPERATE VALUE.
A specified functioning value at which all relays meeting the specifications must operate. Also known as relay pick-up or pull-in value.
RELAY MUST-RELEASE VALUE.
A specified functioning value at which all relays meeting the specifications must release. Also known as relay drop-out value.
RELEASE TIME.
The time between the removal of the relay coil voltage and the stabilized opening of the relay contacts.
RELIABILITY.
The ability of a device to perform within the desired range over a measured period of time.
REMOTE INPUT COUPLER.
The Keithley Model 5951 Remote Input Coupler is a device that connects the 595 Quasistatic C-V Meter and the 590/100k/1M C-V Analyzer together to perform simultaneous C-V. The coupler uses precision RLC circuits to combine the test signals from and route the displacement current to the two meters.
REPEATABILITY.
The ability of an instrument to measure the same input to the same value over a short period of time and over a narrow temperature range.
RESISTANCE INSERTION.
A current measuring technique where a known resistor is connected in series with the circuit to be measured. The voltage drop across the resistor is proportional to the unknown current.
RESISTIVITY.
The geometry independent parameter of a material that determines the relationship between the current through it and the current across it. Resistance of a cylinder of material is:

resistance = resistivity * (length / area)

RESOLUTION.
The smallest value of input (or output) signal, other than zero, that can be measured (or sourced) and displayed. Also called sensitivity or minimum resolvable quantity.
RESOLUTION (DATA ACQUISITION).
The smallest signal increment that can be detected by a measurement system. It is usually specified in "bits."
RESPONSE TIME.
For a measuring instrument, the time between application of a step input signal and the indication of its magnitude within a rated accuracy. For a sourcing instrument, the time between a programmed change and the availability of the value at its output terminals. Also known as Settling Time.
RISE TIME.
The time required for a signal to change from a small percentage (usually 10%) to a large percentage (usually 90%) of its peak-to-peak amplitude. See also FALL TIME.
RMS RESPONDING.
A measurement where the displayed value is equal to the root-mean-square (rms) of the input signal, for all input waveforms having components within the specified frequency range and crest factor limit.
ROW.
As viewed on the schematic of a matrix relay card, the horizontal signal lines or a horizontal group of relays.

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S-PARAMETER CABLE CORRECTION.
A method of correcting for errors in high frequency capacitance measurements due to cables connecting the device under test (DUT) to the instrument. In this method, the cable impedance is measured by a network analyzer and transmitted to the instrument by GPIB. The instrument uses the impedance parameters to correct for cable errors.
SAMPLE.
A value that is read from or written to one channel.
SAMPLE DRAW METHOD (GAS MONITORING).
Air samples are drawn from the point of measurement into the detector head across the sensor, using a diaphragm or eductor pump.
SAMPLED C-T.
Capacitance vs. time measured by applying a stimulus (usually a voltage step) repeatedly ,then sampling the capacitance response at progressively longer intervals after the step in each transient. After sampling, an average transient is reconstructed in software.
SAMPLE RATE.
The rate at which a continuous-time signal is sampled. It is frequently expressed as samples/sec (S/s), kilosamples/sec (kS/s), or Megasamples/sec (MS/s).
SATURATION CURRENTS. (PARAMETRIC TESTING)
A CMOS device parameter. Drain current at maximum drain and gate voltages.
SCAN.
Sequential connecting (usually break-before-make) of one instrument to multiple devices under test or multiple instruments to one device under test. See also MULTIPLEX.
SCAN (DATA ACQUISITION)
Sample a group of channels once at the acquisition or burst-mode rate; also can refer to a group of channels. These channels may be sequential (start to stop channel specified) or nonsequential (channel-gain queue used).
SCAN RATE.
The rate at which a group of channels is sampled, measured from the start of one scan to the start of the next.
SCHOTTKY DIODE.
A junction or barrier formed by the direct contact of semiconductor materials with a metal. This type of contact rectifies signals and may also exhibit some resistance.
SCRIBE AND BREAK.
The procedure used to separate a processed wafer into individual ICs. Narrow channels between individual ICs are mechanically weakened by scratching with a diamond tip (scribe), sawing with a diamond blade, or burning with a laser. The wafer is mechanically stressed and broken apart along the channels (called scribe lines), thereby separating the individual ICs (dice). Test structures are sometimes placed in scribe lines.
SEMICONDUCTOR.
An element such as silicon or germanium or a compound like GaAs that has an intermediate band gap. Unlike metals that freely conduct and insulators that do not conduct charge, semiconductors selectively conduct charge through the movement of holes and electrons.
SEMICONDUCTOR BANDGAP.
The amount of energy needed to move an electron in a semiconductor material from the top of the valence band to the bottom of the conduction band. In silicon, this is about 1.12V.
SENSITIVITY.
See RESOLUTION.
SERIES RC MODEL.
Interpretation of the real and imaginary components of admittance measured by a capacitance meter as resistance in series with capacitance.
SERIES RESISTANCE.
The resistance between the substrate contact to an MIS device and the MIS capacitor. This resistance is increased when substrate doping is low or backside contact is poor.
SETTLING TIME.
For a measuring instrument, the time between application of a step input signal and the indication of its magnitude within a rated accuracy. For a sourcing instrument, the time between a programmed change and the availability of the value at its output terminals. For a switching card, the time required for establishing relay connections and stabilizing user circuits. Also known as Response Time.
SETTLING TIME (DATA ACQUISITION)
Time it takes for a voltage to settle and remain within a specified error band around the final value.
SHEET RESISTANCE.
A measure of the resistance of a film of material related to its resistivity divided by the film thickness. It is often measured using a four-point probe and is directly related to the average doping in the film.
SHEET RESISTANCES. (PARAMETRIC TESTING)
A CMOS or bipolar device parameter. Resistance per square of conductor.
SHIELDING.
A metal enclosure for the circuit being measured or a metal sleeve surrounding wire conductors (coax or triax cable) to lessen interference, interaction, or current leakage. The shield is usually grounded.
SHORT-TERM ACCURACY.
The limit that errors will not exceed during a 24-hour period of continuous operation. Unless specified, no zeroing or adjustments of any kind are permitted. It is expressed as a percentage of reading (or sourced value) plus a number of counts over a specified temperature range.
SHUNT CAPACITANCE LOADING.
The effect on a capacitance meter of capacitance, such as from cables or fixtures, between the meter input or output terminals and guard (sometimes referred to as common). Shunt capacitance reduces the measured device current. Therefore, the measured device capacitance is smaller.
SIGNAL/NOISE RATIO.
The ratio of the maximum signal that can be measured to the level detected with no signal present (noise level). It is expressed in decibels.
SILICON.
The most common elemental semiconductor. From silicon crystals that are grown and sliced into wafers.
SILICON DIOXIDE.
See OXIDE.
SIMULTANEOUS C-V.
A technique commercialized by Keithley Instruments for measuring quasistatic and high-frequency C-V in one voltage sweep. This eliminates errors due to misalignment between the two during analysis.
SIMULTANEOUS SAMPLE-AND-HOLD.
Operation in which the analog input channels are sampled at the same time and the values held until sequentially read by a scanning A/D system.
SINGLE-ENDED.
The condition where the low terminal of a two-terminal instrument is connected to a specific reference point, such as power line common, earth ground, or circuit common.
SINGLE-ENDED INPUT (DATA ACQUISITION).
An analog input with one input terminal whose value is measured with respect to a common ground. See also DIFFERENTIAL INPUTS.
SLAVE.
A mainframe that is externally connected to a controlling mainframe (master). A slave unit adds capacity or functions to the master. See also MASTER and MAINFRAME.
SLEW RATE.
The maximum charge rate of the signal sampling capacitor in the sample and hold circuit of an A/D converter. It is expressed in volts/microsecond.
SMALL SIGNAL LEVEL.
The amplitude of AC test signal voltage producing a linear response of the device under test. In other words, over the small signal range, the shape of the device response curve can be assumed to be linear without distorting the results. For MIS devices, this is usually 50mV or less.
SOI.
Silicon-On-Insulator. A composite structure consisting of an active layer of silicon deposited on an insulating material. The insulator can be sapphire, silicon dioxide, silicon nitride, or even an insulating form of silicon itself.
SOFTWARE TRIGGER.
A programmed event that starts an operation such as data acquisition.
SOLVENT.
A material that is capable of dissolving another chemical to form a uniformly dispersed mixture (solution).
SOURCE IMPEDANCE.
The combination of resistance and reactance that a source presents to the input terminals of a measuring instrument.
SOURCE-MEASURE UNIT (SMU).
An electronic instrument that sources and measures DC voltage and current. Generally, SMUs have two modes of operation: source voltage and measure current, or source current and measure voltage. Programmable features can include: constant or sweep source, measurement delays, and compliance levels. Also known as a source/monitor unit or a stimulus/measurement unit.
SOURCE TERMINAL.
Along with the gate and drain, one of the three terminals of an FET.
SPECTRAL PURITY.
A description of the distortion components of an oscillator's output signal at a specified amplitude and load. Includes total harmonic distortion, harmonics, and spurious components.
SPREADING RESISTANCE PROFILER (SRP).
A measurement system that measured carrier concentration by beveling the wafer (grinding it at an angle), then measuring resistance with two probes.
SPURIOUS COMPONENTS.
Undesired signals in the output of a signal generator that have a defined amplitude and frequency. They are not harmonically related to the fundamental frequency. Specified as decibels below the carrier frequency.
STAIRCASE WAVEFORM.
A waveform in which the voltage is incremented in uniform steps from the start voltage to the stop voltage.
STANDOFF POTENTIAL.
The breakdown voltage across relay contacts.
STRESS GRADIENT.
Stress gradients are produced between layers due to different thermal coefficients of expansion between the layers.
STRESS TEMPERATURE, TIME, AND VOLTAGE.
See BIAS TEMPERATURE STRESS TEST.
STRETCHOUT.
An effect caused by interface traps, which make the C-V curve take more voltage for the same curve shape. Before quasistatic C-V and simultaneous C-V were predominant, this phenomenon was used to measure Dit using the "Terman" method.
SUBROUTINE.
A set of software instructions executed by a single line of code.
SUBSTRATE.
The underlying material upon which a device circuit or epitaxial layer is fabricated. This term also applies to the MIS capacitor, which has only two terminals: the gate and substrate.
SUBTHRESHOLD SLOPES, LINEAR. (PARAMETRIC TESTING)
Slope of log (drain current) vs. gate voltage, small drain voltage.
SUBTHRESHOLD SLOPES, SATURATION (PARAMETRIC TESTING)
Slope of log (drain current) vs. gate voltage, large drain voltage.
SURFACE GENERATION VELOCITY.
A parameter derived from C-t using Zerbst analysis. This parameter is related to generation of electron-hole pairs at the semiconductor surface, whereas generation lifetime pertains to generation in the bulk semiconductor material.
SURFACE LEAKAGES. (PARAMETRIC TESTING)
A CMOS or bipolar device parameter or a yield parameter. Leakage per unit surface area.
SURFACE POTENTIAL.
For our purposes, this term is equivalent to "band bending."
SWITCH.
Connecting one input to one output. Also known as actuate.
SWITCH CARD.
A type of card with independent and isolated relays for switching inputs and outputs on each channel.
SWITCHED CURRENT.
The maximum current level that can be reliably handled while opening and closing contacts. See also CARRY CURRENT.
SWITCHING MAINFRAME.
A switching instrument that operates according to user commands to connect signals among sourcing and measuring instruments and devices under test. A mainframe is also referred to as a scanner, multiplexer, matrix, or programmable switch.
SYNCHRONOUS.
In hardware, it is an event that occurs in a fixed time relationship to another event. In software, it refers to a function that begins an operation and returns to the calling program only when the operation is complete.

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TEMPERATURE COEFFICIENT.
A change in reading (or sourced value) with a change in temperature. It is expressed as a percentage of reading (or sourced value), plus a number of counts per degree change in temperature.
TEMPERATURE COEFFICIENT OF RESISTANCE.
The amount of resistance change of a material per degree of temperature change.
TEST STRUCTURE.
A device manufactured on a wafer expressly for the purpose of testing.
THERMOCOUPLE.
A temperature sensor created by joining two dissimilar metals. This junction creates a small voltage as a function of the temperature.
THERMOELECTRIC VOLTAGE.
Voltages resulting from temperature differences within a measuring circuit or when conductors of dissimilar materials are joined together. Also known as thermal EMF or thermal offset. See CONTACT POTENTIAL.
THIN FILM.
A thin layer of material grown or deposited on a substrate.Typically, layer thickness is measured in tens to thousands of angstroms for insulators and microns for metals.
THRESHOLD VOLTAGE (VT).
The gate voltage needed to turn on a MOS enhancement-mode device.
THRESHOLD VOLTAGES. (PARAMETRIC TESTING)
A CMOS device parameter. Voltage at 40 nA*W/L, or extrapolation from maximum linear slope.
THROUGHPUT.
The maximum rate at which a data conversion system can perform repetitive conversions within a specified accuracy. It is determined by summing the various times required for each part of the conversion system and then taking the inverse of this time. The throughput rate takes into account the total time required to process a signal and store the value in either on-board or system memory.
TIMEBASE ACCURACY.
A measure of how closely the internal timebase of an instrument tracks a known time standard.
TIMING JITTER.
The short-term variation of the time period between sample points.
TLV-C.
Threshold Limit Value - Ceiling is the concentration that should not be exceeded during any part of the working exposure.
TLV-STEL.
Threshold Limit Value - Short-Term Exposure Limit is a 15 minute time weighted average exposure that should not be exceeded at any time during a work day, even if the 8 hour TWA is within the TLV. Exposures at the STEL concentration should not be repeated more than 4 times a day and there should be at least 60 minutes between successive exposures at the STEL.
TLV-TWA.
Threshold Limit Value - Time Weighted Average is the time weighted average concentration for a normal 8 hour work day and a 40 hour work week, to which nearly all workers may be exposed without adverse effect.
TOTAL HARMONIC DISTORTION.
The percentage of harmonic distortion present in an output signal over a specified frequency range.
TOXICITY.
Ability of a substance to cause harmful effects.
TRANSCONDUCTANCE.
The ratio of the incremental change in the output current of any amplifying circuit or device to the incremental change of input voltage causing it, when the output voltage is held constant.
TRANSCONDUCTANCES. (PARAMETRIC TESTING)
A CMOS device parameter. Change in drain current/change in gate voltage.
TRANSFER ACCURACY.
A comparison of two nearly equal measurements over a limited temperature and time. It is expressed in ppm.
TRANSFER RATE.
The rate at which data is transferred to or from memory.
TRANSISTOR.
A semiconductor device in which a small control signal is used to control a larger current flow.
TRANSISTOR BREAKDOWN. (PARAMETRIC TESTING)
A bipolar device parameter. Primarily collector to emitter breakdown, base open.
TRIGGER (INSTRUMENTATION).
An external stimulus that initiates one or more instrument functions. Trigger stimuli include: an input signal, the front panel, an external trigger pulse, and IEEE-488 bus X, Talk, and GET triggers.
TRIGGER (DATA ACQUISITION).
An event that starts or stops an operation. A trigger can be a specific analog, digital, or software condition. See also ANALOG TRIGGER and DIGITAL TRIGGER.
TRIGGER CONDITIONS.
Refers to trigger sensitivity, polarity, etc.
TRIGGER HYSTERESIS.
Applies only to analog triggers. It helps prevent noise from triggering an operation or event. For a positive-edge trigger, the analog signal must be above the specified voltage level by at least the amount of the hysteresis value before the trigger occurs. For a negative-edge trigger, the analog signal must be below the specified voltage level by at least the amount of the hysteresis value before the trigger can occur.
TRIGGER JITTER.
The short-term variation of the time period between a trigger event and the first sample point.
TRIGGER LATENCY.
The fixed time offset between the trigger event and the first sample point.
TRIGGER MODE.
Refers to when data acquisition begins and ends in relationship to the trigger. Trigger modes include normal-trigger, pre-trigger, about-trigger, post-trigger, trigger-to-trigger, and trigger-to-about-trigger.
TRIGGER POLARITY.
For edge-sensitive triggers: trigger polarity defines whether the trigger occurs when the signal is rising (positive direction) or falling (negative direction). For level-sensitive triggers: trigger polarity defines whether the trigger occurs when the signal is above a level (positive) or below a level (negative).
TRIGGER SENSITIVITY.
Refers to edge and/or level of a trigger. For analog triggers, trigger sensitivity defines whether the trigger occurs on a transition across a specified value (edge) or whether the trigger occurs when it is above or below a specified value (level). For digital triggers, trigger sensitivity defines whether the trigger occurs on a transition from one state to another state (edge) or whether the trigger occurs when it is at a specified value (level).
TTL.
Abbreviation for transistor-transistor-logic. A popular logic circuit family that uses multiple-emitter transistors. A low signal state is defined as a signal 0.8V and below. A high signal state is defined as a signal +2.0V and above.
TUNNELING CURRENT.
Tunneling current is classically forbidden current across an insulator that is predicted by the quantum mechanics model.
TURNER TEST STRUCTURES.
Structures that are specifically designed for high speed process monitoring of product reliability factors. Each structure is tailored to conform to a fab's specific process and design rules.
TWO-TERMINAL RESISTANCE MEASUREMENT.
A measurement where the same current flows through the unknown and the test leads.

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UNIPOLAR.
An analog signal range that is always positive (through zero.)


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VALENCE BAND.
The energy levels of the electrons in he outermost shell of the atoms making up a solid material.
VAPOR.
A gaseous form of a material that is normally a solid or liquid at room temperature and pressure.
VAPOR DENSITY.
The density of a vapor compared to the density of an equal amount of air.
VARIABLE FREQUENCY.
Frequency settable over a range. This term is applied to a capacitance meter that offers a choice of test signal frequencies from so many that it is essentially continuously adjustable.
VIA.
A plated hole used to provide low inductance connections on an IC. A via may be formed through the dielectric layer on the top of a slice to interconnect two metallization patterns or may be formed through the back of a slice containing FETs where a low inductance earth is required.
VOLTAGE BURDEN.
The voltage drop across the resistor for the resistance insertion technique of current measurement.
VOLTAGE STANDING WAVE RATIO (VSWR).
For a switching card, the loss due to the mismatch introduced into the signal by the card contacts and conductors. Expressed as a ratio of the highest voltage to the lowest voltage found in the signal.

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WAFER.
A slice from an ingot (material prepared by solidification from a melt) on which semiconductor devices are made.
WAFER PROBING.
An electrical test of devices on the wafer, using small probes to make contact with the metallized pads on the die.
WARM-UP TIME.
The time required after power is applied to an instrument to achieve rated accuracy at referenced conditions.
WORD.
The standard number of bits that a processor manipulates at one time. Microprocessors typically use 16-, or 32-bit words. (Or 2 bytes and 4 bytes respectively.)
WORK FUNCTION.
The minimum energy required to remove an electron from the Fermi level of a material into field-free space. Work function is normally expressed in electron volts.

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YIELD.
The ratio of good units obtained divided by the total units produced. It is the percent of wafers, dice, or packaged units conforming to specifications.

Z

ZERO OFFSET.
The reading (desired or undesired) that occurs when the input terminals of a measuring instrument are shorted.
ZERBST PLOT.
A plot used to extract generation lifetime and surface generation velocity from C-t data. This plot is derived from d(1/C2) / dt vs. depletion width.
ZIEGLER METHOD.
See MAJORITY CARRIER CORRECTION METHOD.

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